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CS4812 Fixed Function Multi-Effects Audio Processor
Features
l DSP
Description
The CS4812 is a complete audio effects processing system on a chip. This device includes a proprietary 24bit audio processing engine with considerable on-chip RAM, two ADCs and two DACs. A full-featured serial control port allows interfacing to an external host microcontroller. Other features such as single +5V operation simplify system design. The CS4812, combined with Crystal effects firmware, is the ideal solution for a variety of effects processing applications where user parameter control is desired. The Crystal effects firmware provides a messaging protocol for the serial control port that allows an external microcontroller to have real-time parameter control over the audio effects. The complete processor and effects solution may be evaluated with the CDB4812 demonstration board. The CDB4812 demonstrates a host of mono electric guitar effects including a digital spring reverb, delay, chorus, flange and tremolo with parameter adjustment capability. Please refer to AN195 for more information on application firmware for the CS4812.
for embedded reverb/effects applications
- 24-bit Audio Processing Engine - No External RAM required - Two 24-bit ADCs with 100 dB Dyn. Range - Two 24-bit DACs with 100 dB Dyn. Range
l Mono
Guitar or Mixer Effects firmware included l Real time parameter control via messaging protocol l Serial Control Port for microcontroller interface l Single +5V supply operation l 100-pin Metric Quad Flat Package (MQFP)
ORDERING INFO CS4812-KM -10 to +70C 100-pin MQFP CDB4812 Electric Guitar Effects w/ Parameter Controls.
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Advance Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2001 (All Rights Reserved)
JUL `01 DS291PP3 1
CS4812
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 14 3. FUNCTIONAL DESCRIPTION ............................................................................................... 17 3.1 Overview .......................................................................................................................... 17 3.2 Analog Inputs ................................................................................................................... 17 3.2.1 Line Level Inputs ................................................................................................. 17 3.2.2 Digital High Pass Filter ........................................................................................ 18 3.3 Analog Outputs ................................................................................................................ 18 3.3.1 Line Level Outputs .............................................................................................. 18 3.4 Clock Generation ............................................................................................................. 19 3.4.1 Clock Source ....................................................................................................... 19 3.5 Serial Control Port ............................................................................................................ 19 3.5.1 SPI Bus ............................................................................................................... 19 3.5.1.1 SPI Master Mode ................................................................................ 20 3.5.1.2 SPI Slave Mode .................................................................................. 20 3.5.2 I2C Bus ................................................................................................................ 23 3.5.2.1 I2C Master Mode ................................................................................. 23 3.5.2.2 I2C Slave Mode ................................................................................... 24 3.6 Boot Modes ...................................................................................................................... 26 3.6.1 AutoBoot ............................................................................................................. 26 3.6.2 HostBoot ............................................................................................................. 26 3.7 Resets ............................................................................................................................. 27 4. POWER SUPPLY AND GROUNDING ................................................................................... 28 5. PIN DESCRIPTIONS .............................................................................................................. 29 6. PARAMETER DEFINITIONS .................................................................................................. 33 7. PACKAGE DIMENSIONS ...................................................................................................... 34
LIST OF FIGURES
Figure 1. SPI Control Port Slave Mode Timing .......................................................... 8 Figure 2. SPI Control Port Master Mode (AutoBoot) Timing ..................................... 9 Figure 3. I2C(R) Control Port Slave Mode Timing ...................................................... 11 Figure 4. I2C(R) Control Port Master Mode (AutoBoot) Timing .................................. 12 Figure 5. Typical Connection Diagram, Control Port Slave Mode ........................... 14 Figure 6. Typical Connection Diagram, Control Port I2C Master Mode ................... 15 Figure 7. Typical Connection Diagram, Control Port SPI Master Mode .................. 15 Figure 8. Typical Connection Diagram, Control Port I2C Slave Mode ..................... 16 Figure 9. Typical Connection Diagram, Control Port SPI Slave Mode .................... 16 Figure 10.Recommended Line Input Buffer .............................................................. 17
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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Figure 11.Single Ended Input ................................................................................... 18 Figure 12.Butterworth Output Filters ........................................................................ 18 Figure 13.Output Mute Circuit .................................................................................. 19 Figure 14.Control Port Timing, SPI Master Mode AutoBoot ..................................... 20 Figure 15.Control Port Timing, SPI Slave Mode Write ............................................. 20 Figure 16.SPI Slave Write Flow Diagram ................................................................. 21 Figure 17.Control Port Timing, SPI Slave Mode Read ............................................. 21 Figure 18.SPI Slave Mode Read Flow Diagram........................................................ 22 Figure 19.SPI Slave Mode Read Flow Diagram with DSP REQ .............................. 22 Figure 20.Control Port Timing, I2C Master Mode AutoBoot ..................................... 23 Figure 21.I2C Slave Mode Write Flow Diagram ........................................................ 24 Figure 22.Control Port Timing, I2C Slave Mode Write .............................................. 24 Figure 23.Control Port Timing, I2C Slave Mode Write .............................................. 24 Figure 24.I2C Slave Mode Read Flow Diagram ....................................................... 25 Figure 25.I2C Slave Mode Read Flow Diagram with DSP REQ ............................... 26 Figure 26.HostBoot Flow Diagram ........................................................................... 27 Figure 27.CS4812 Suggested Layout ...................................................................... 28 Figure 28.Pin Assignments ...................................................................................... 29
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CS4812
1. CHARACTERISTICS AND SPECIFICATIONS
ADC CHARACTERISTICS (TA = 25C; VA, VD = + 5V; -1 dB Full Scale Input Sine wave,
997 Hz; Fs = 48 kHz; XTI = 12.288 MHz (PLL disabled). Measurement Bandwidth is 20 Hz to 20 kHz.) Parameters Analog Input Characteristics ADC Conversion Dynamic Range Total Harmonic Distortion + Noise (PLL enabled) Interchannel Isolation Interchannel Gain Mismatch Offset Error (with high pass filter enabled) Full Scale Input Voltage (Differential) Gain Drift Input Resistance Input Capacitance CMOUT Output Voltage Common Mode Rejection Ratio Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency High Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Notes: 1. Referenced to typical full-scale differential input voltage (2 Vrms). 2. Bench tested only. 3. Filter characteristics scale with output sample rate. 4. Group delay for Fs = 48 kHz, tgd = 15/48 kHz = 313 s. 5. Measured using differential analog input circuit, see Figure 10. 6. Filter Response is not tested but guaranteed by design. -3dB (Note 3) -0.14dB (Note 3) @ 20 Hz (Note 3) 3.7 20 10 0 Hz Hz Degree dB (Note 2) (Note 4) CMRR tgd tgd (Note 2) (Note 6) Stereo Audio channels (A weighted, Note 5) (unweighted, Note 5) (Note 1,5) (Note 1,2,5) THD+N 16 93 90 1.9 10 100 97 -92 -92 90 0.1 2.0 100 2.3 60 15/Fs 0 24 -87 0 2.1 15 Bits dB dB dB dB dB LSB Vrms ppm/C k pF V dB s s Symbol Min Typ Max Units
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DAC CHARACTERISTICS (TA = 25C; VA, VD = + 5V; -1 dB Full Scale Output Sine wave,
997 Hz; Fs = 48 kHz; XTI = 12.288 MHz (PLL disabled). Measurement Bandwidth is 20 Hz to 20 kHz.) Parameters DAC Resolution Dynamic Range Interchannel Isolation Interchannel Gain Mismatch Offset Voltage (differential) Offset Voltage (V+/V- relative to CMOUT) Full Scale Output Voltage Gain Drift Out of Band Energy Analog Output Load Resistance Capacitance tgd CCIR-2K (Note 7) (Note 7) (Differential) (Note 2) (Fs/2 to 2Fs, Note 2) (DAC not muted, A weighted) THD+N Total Harmonic Distortion + Noise Symbol Min 16 95 1.9 10 Typ 100 -90 90 0.1 -20 5 -45/-25 2.0 100 -60 16/Fs 74 200 1 50 Max 24 -85 2.1 100 Units Bits dB dB dB dB mV mV Vrms ppm/C dBFS k pF s dB mA mA dB
Analog Output Characteristics - Minimum Attenuation, 10 k, 100 pF load; unless otherwise specified.
Group Delay (Fs = Input Sample Rate) Analog Loopback Performance Signal-to-Noise Ratio (CCIR-2K weighted, -20 dB input) Power Supply Power Supply Current Power Supply Rejection Operating Power Down (Note 8)
(1 kHz, 10 mVrms, Note 2)
Notes: 7. Measured with DAC calibration disabled. 8. Measured with XTI clock disabled.
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CS4812
SWITCHING CHARACTERISTICS (TA = 25 C; VA, VD = +5V, CL = 30 pF)
Parameters Audio ADC's & DAC's Sample Rate XTI Frequency XTI = 128Fs, 256Fs, 512Fs XTI Duty Cycle XTI = 128Fs, 256Fs, 512Fs XTI Jitter Tolerance RST Low Time (Note 10) (Note 9) Symbol Fs Min 30 3.84 40 500 Typ 500 Max 50 25.6 60 Units kHz MHz % ps ns
Notes: 9. Guaranteed by characterization but not tested. 10. On power-up, the CS4812 RST pin should be asserted until the power supplies have reached steady state.
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SWITCHING CHARACTERISTICS - CONTROL PORT - SPI SLAVE
(TA = 25 C; VA, VD = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 30 pF) Parameter SPI Slave Mode (SPI/I2C = 0, SCPM/S = 0, Note 14) CCLK Clock Frequency CCLK Low Time CCLK High Time Rise Time of Both CDIN and CCLK Lines Fall Time of Both CDIN and CCLK Lines Setup Time CDIN to CCLK Rising Hold Time CCLK Rising to CDIN Time from CCLK edge to CDOUT Valid Rise Time for CDOUT Fall Time for CDOUT CS Falling to CCLK Rising Time from CCLK Falling to CS Rising High Time Between Active CS Time from CCLK Rising to REQ Rising Rise Time for REQ Fall Time for REQ (Note 13) (Note 11) (Note 12) fsck tscl tsch tr tf tcdisu tcdih tscdov tcdor tcdof tcss tsccsh tcsht tscrh trr trf 66 66 40 15 20 0 1 6 100 100 45 25 25 2*DSPCLK+10 100 100 MHz ns ns ns ns ns ns ns ns ns ns ns s ns ns ns Symbol Min Max Unit
Notes: 11. Data must be held for sufficient time to bridge 100 ns transition time of CCLK. 12. CDOUT should NOT be sampled during this time period. 13. DSPCLK frequency is twice the DSP instruction rate. 14. Timing is guaranteed by characterization. Production test guarantees functionality.
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8
t sccsh t csht 5 7 6 t sch A5 A0 R/W MSB LSB A6 MSB t scdov t scdov trh LSB tri-state t cscdo
CS (input)
t css
t scl
SCL/CCLK (input)
tr
tf
CDIN
A6
t cdisu t cdih
CDOUT
*
REQ (output) t scrh
t rf
* See section 3.5.1.2 for a detailed explanation of REQ behavior
Figure 1. SPI Control Port Slave Mode Timing
CS4812
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CS4812
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MASTER
(TA = 25C, VA, VD = 5V; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30 pF) Parameter CCLK Clock Frequency CCLK Low Time CCLK High Time CCLK Rise Time CCLK Fall Time RST rising to CS falling CS High Time Between Transmissions CS Falling to CCLK Edge CS Falling to CDOUT valid CCLK Falling to CDOUT valid CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CS rising (Note 16) (Note 16) (Note 15) Symbol fsck tscl tsch tr2 tf2 tsrs tcsh tcss tdv tpd tdsu tdh tclcs Min 37 5 80 80 40 Typ Fs 1/(2*Fs) 1/(2*Fs) 12 12 42 Max 50 100 Units kHz ns ns ns ns s s s ns ns ns ns ns SPI Master (AutoBoot) Mode (SPI/I2C = 0, SCPM/S = 1, Note 14)
Notes: 15. Depending on the input clock configuration, CCLK may be up to 2*Fs temporarily during AutoBoot after RST is de-asserted and before the control port registers have been initialized. 16. Measured with a 2.2 k pull-up resistor to VD.
RST
t srs
CS t css CCLK t r2
CDIN
t scl
t sch
t clcs
t csh
t f2
t dsu t dh CDOUT
t dv
t pd
Figure 2. SPI Control Port Master Mode (AutoBoot) Timing
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CS4812
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C(R) SLAVE
(TA = 25 C; VA, VD = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 30 pF) Parameter I2C(R) Slave Mode (SPI/I2C = 1, SCPM/S = 0) (Note 17) SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) SCL Low Time SCL High Time RST rising to start condition SDA Hold Time from SCL Falling Rise Time of Both SDA and SCL Fall Time of Both SDA and SCL SCL Falling to CS4812 ACK SCL Falling to SDA Valid During READ Time from SCL Rising to REQ Rising Rise Time for REQ Fall Time for REQ Setup Time for Stop Condition Setup Time for Repeated Start (Note 20) (Note18) (Note 19) fscl tbuf thdst tlow thigh tsrs thdd tr tf tsca tscsdv tscrh trr trf tsusp tsust 4.7 4.0 4.7 4.0 1 0 4.7 4.7 100 1 300 1.3 1.5 2*DSPCLK+10 100 100 kHz s s s s ms s s ns s s ns ns ns s s Symbol Min Max Units
Notes: 17. Use of the I2C bus interface requires a license from Philips. I2C is a registered trademark of Philips Semiconductors. 18. Not tested. 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. 20. DSPCLK frequency is twice the DSP instruction rate.
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stop A6 R/W ACK t scsdv 1 8 0 6 7 6 7 8 t sud 0 A5 A0 MSB LSB ACK t hdst t low t high tr tf t hdd t sca t rr tsusp
stop
start
SDA
t buf
SCL/CCLK (input)
*
REQ t scrh
t rf
* See section 3.5.2.2 for a detailed explanation of REQ behavior
Figure 3. I2C(R) Control Port Slave Mode Timing
CS4812
11
CS4812
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C(R) MASTER (TA = 25C;
VA, VD = 5V; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30 pF) Parameter I2 (R) SCL Clock Frequency Clock Low Time Clock High Time Bus Free Time Between Transmissions RST rising to start condition Start Condition Hold Time Setup Time for Repeated Start Condition SDA Setup Time to SCL Rising SDA Hold Time from SCL Falling SCL falling to SDA Output Valid SCL and SDA Rise Time SCL and SDA Fall Time Setup Time for Stop Condition (Note 24) (Note 24) (Note 23) (Note 22) Symbol fscl tlow thigh tbuf tirs thdst tsust tsud thdd tcldv tr tf tsusp Min 4.7 4.0 13.5 250 0 4.7 Typ Fs 1/(2*Fs) 1/(2*Fs) 22 Max 1.5 1 300 Units kHz s s s s s s ns s s s ns s
C Master (AutoBoot) Mode (SPI/I2C = 1, SCPM/S = 1) (Note 21)
Notes: 21. Use of the I2C bus interface requires a license from Philips. I2C is a registered trademark of Philips Semiconductors. 22. Depending on the input clock configuration, CCLK may be up to 2*Fs temporarily during AutoBoot after RST has been de-asserted and before the control port registers have been initialized. 23. Data must be held for sufficient time to bridge the worst case fall time of 300 ns for CCLK/SCL. 24. For both SDA transmitting and receiving.
RST t irs Stop SDA t buf
SCL
(output)
Start
t
cldv
Repeated Start
Stop
t hdst
t high
t
hdst
tf
t susp
t
low
t
hdd
t sud
t sust
tr
Figure 4. I2C(R) Control Port Master Mode (AutoBoot) Timing
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CS4812
ABSOLUTE MAXIMUM RATINGS (All voltages with respect to AGND = DGND = 0V.)
Parameters Power Supplies Input Current Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Digital Analog (Note 25) (Note 26) (Note 26) (Power Applied) Symbol VD VA Min -0.3 -0.3 -0.7 -0.7 -55 -65 Typ Max 6.0 6.0 10.0 (VA)+0.7 (VD)+0.7 +125 +150 Units V V mA V V C C
Notes: 25. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 26. The maximum over or under voltage is limited by the input current. Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(All voltages with respect to AGND = DGND = 0V.) Parameters Power Supplies |VA - VD| < 0.4V Operating Ambient Temperature Digital Analog Symbol VD VA TA Min 4.75 4.75 -10 Typ 5.0 5.0 25 Max 5.25 5.25 70 Units V V C
DIGITAL CHARACTERISTICS (TA = 25 C; VA, VD = 5V)
Parameters High-level Input Voltage Low-level Input Voltage High-level Output Voltage at I0 = -2.0 mA Low-level Output Voltage at I0 = 2.0 mA High-level Input Voltage Low-level Input Voltage Input Leakage Current Output Leakage Current (except XTI) (except XTI) (except XTO) (except XTO) (XTI) (XTI) (Digital Inputs) (High-Z Digital Outputs) Symbol VIH VIL VOH VOL VIH VIL Min 2.8 -0.3 (VD)-1.0 2.8 Typ Max (VD)+0.3 0.8 0.4 2.3 10 10 Units V V V V V V A A
SWITCHING CHARACTERISTICS - PROGRAMMABLE I/O
(TA = 25 C; VA, VD = 5V 5%; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30 pF) Parameters Output Rise Time Output Fall Time Symbol trpo tfpo Min Typ 200 200 Max Units ns ns
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CS4812
2. TYPICAL CONNECTION DIAGRAMS
Ferrite Bead + 1 F
0.1 F + 1 F 0.1 F
+5 V
A
A
D
D
12 18 88 VA 1..3
86 ANALOG FILTER AIN1L+ AIN1LAIN1R+
43 65
VD 1..2
AOUT1+ AOUT17 8 ANALOG FILTER
87
90
ANALOG FILTER
AOUT2+
9 10 ANALOG FILTER
91
AIN1R-
AOUT2-
To Optional Input and Output Buffers
92 1 F
A A
CMOUT
RES-NC RES-NC
14
15
0.1 F
CS4812
39 93 OVL CMFILT+
RES-NC RES-NC RES-NC RES-NC RES-NC
16
17 20 21
+
22
23
1 F
0.1 F
94
CMFILT-
RES-NC RES-NC
57
58 59
A
2.2 K
D Q
VD VD2.2 K 63
RES-NC RES-NC
SCL/CCLK SDA/CDOUT
AD0/CS AD1/CDIN REQ CLKOUT
RES-NC RES-NC
60
61 95 97 VD
Program ROM or Serial EEPROM
74HC74
62 68 67 71 47
RES-NC RES-NC
Microcontroller
RES-VD
73
RS 69 70 Mode/Reset Circuit
D
SPI/I2C SCPM/S
RES-DGND RES-DGND RES-DGND RES-DGND
32
34
36 38 48 82 83 96
D
72
RST
RESET
RES-DGND 41 Control/ Monitor Circuitry 40 37 35 PIO0 PIO1 PIO2 RES-DGND RES-DGND RES-DGND
PIO3
AGND1..4 1113 19 89 XTO XTI 46 45 1 M Optional External Clock Input instead of Crystal
DGND1..4 42 44 64 66
RS = 33 All unused inputs should be tied to ground.
A
D
39 pF 39 pF
D D
Figure 5. Typical Connection Diagram, Control Port Slave Mode
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CS4812
VD VD 2.2 K 2.2 K CS4812 63
SCL/CCLK
SDA/CDOUT AD0/CS
62
A0 A1 A2
D
I 2C EEPROM
68
67 71 69 70
AD1/CDIN
REQ SPI/I2C SCPM/S
VD
D
Reset Circuit
RESET
72
73
RST
PLLEN
Figure 6. Typical Connection Diagram, Control Port I2C Master Mode
CS4812 63 62 SCL/CCLK
SPI EEPROM
SDA/CDOUT
AD0/CS AD1/CDIN
68 67 71 VD 69 70
D
REQ
SPI/I2C SCPM/S
Reset Circuit
RESET
72 73
RST
PLLEN
Figure 7. Typical Connection Diagram, Control Port SPI Master Mode
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CS4812
VD 2.2 K VD 2.2 K
CS4812 SDA SCL SDA/CDOUT
D
74HC74
SCL/CCLK
MICRO CONTROLLER RS
CLKOUT AD0/CS AD1/CDIN
GPIO
REQ SPI/I2C SCPM/S
RESET CIRCUIT
D VD
RST PLLEN
Figure 8. Typical Connection Diagram, Control Port I2C Slave Mode
CS4812 MISO CCLK SDA/CDOUT
D
74HC74
SCL/CCLK
MICRO CONTROLLER RS CS MOSI GPIO
CLKOUT AD0/CS AD1/CDIN REQ SPI/I2C SCPM/S
RESET CIRCUIT
D VD
RST PLLEN
Figure 9. Typical Connection Diagram, Control Port SPI Slave Mode
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3. FUNCTIONAL DESCRIPTION 3.1 Overview
The CS4812 is a complete audio subsystem on a chip, integrating an DSP with on-chip RAM, two 24-bit ADCs, two 24-bit DACs, and a serial control port. The sigma-delta ADCs include linear phase digital anti-aliasing filters and only require a single-pole external passive filter. The sigma-delta DACs include analog switchedcapacitor anti-image filters and require an external second or third order active filter that can be easily integrated into an output differential-to-single-ended converter circuit. The serial control port is designed to accommodate I2C(R) or SPI interfaces and can operate in master or slave mode. It allows interfacing to external nonvolatile memory for stand-alone operation or to a host-controller for real-time control. All communications between the DSP and an external EEPROM or host-controller are handled through the serial control port.
3.2 3.2.1
Analog Inputs Line Level Inputs
AINR+, AINR-, AINL+, and AINL- are the line level analog inputs (See Figure 5). These pins are internally biased to the CMOUT voltage of 2.3 V. A DC blocking capacitor placed in series with the input pins allows signals centered around 0 V to be input to the CS4812. Figure 5 shows operation with a single-ended input source. This source may be supplied to either the positive or negative input as long as the unused input is connected to ground through capacitors as shown. When operated with single-ended inputs, distortion will increase at input levels higher than -1 dBFS. If better performance is required, a single-ended-to-differential converter, shown in Figure 10, may be used. It provides unity gain, DC blocking and anti-alias filtering. Inputs may be externally AC or DC coupled. This permits use of the ADCs for input of audio signals or for measurement of DC control voltages. By default, an internal high pass filter removes any DC offsets from both of the ADC inputs. If measurement of DC is required on either of the ADC inputs, then the on-chip high pass filter must be disabled. Analog audio input signals that are DC coupled must be biased at 2.3 V to maintain proper input
4.7 k
10 F
10 k
input signal (2 Vrms max)
+ 10 k 10 k +5 V -
150 AIN -
+
2.2 nf
150 AIN +
+ CMOUT + +
10 f 0.1 F GND
Figure 10. Recommended Line Input Buffer DS291PP3 17
CS4812
150 22 F
CS4812 AIN 2.2 nF
of driving 10 k loads to full scale. These amplifiers internally biased to the CMOUT voltage of 2.3 V. The recommended off-chip analog filter is a second order Butterworth with a 3 dB corner at Fs. A third order Butterworth filter with a -3 dB corner at 0.75 Fs can be used if greater out of band noise filtering is desired. These filters can be easily integrated into a differential-to-single-ended converter circuit as shown in the 2-pole and 3-pole Butterworth filters of Figure 12. The hardware mute circuit referenced in Figure 12 is shown in Figure 13. Hardware muting is recommended on power-up and powerdown.
AIN + 100 F 0.1 F
Figure 11. Single Ended Input
signal swing. DC control input voltages may range from ground to Vcc. ADC output data is in twos-complement binary format. For inputs above full scale, the ADC digital output saturates. The OVL output pin asserts when the analog input is out-of-range.
220 pF 14.0 k 14.0 k 3.24 k +5 V _ + GND 14.0 k AOUT+ 1000 pF
BUFFERED CMOUT
3.2.2
Digital High Pass Filter
AOU T1000 pF
Output Mute Ckt
Line Out
In DC coupled systems, a small DC offset may exist between the input circuitry and the A/D converters. The CS4812 includes a defeatable high pass filter after the decimator to remove these DC components. The high pass filter response is given in "High Pass Filter Characteristics" on page 4 and scales linearly with sample rate. In applications where DC level measurement is required, as would occur when one of the ADC inputs is used for measurement of DC control voltages, the high pass filter may be disabled via a control port register. Note: The high pass filter defeat operates on both ADC inputs simultaneously therefore external DC blocking must be provided in the design of the analog audio input circuit.
3.24 k
14.0 k
220 pF
2-Pole Butterworth Filter
220 pF
14.0k 2.8k 2.8k
+5 V _ + GND Output Mute Ckt Line Out
11.0k
AOU T2200 pF 2200 pF
2.8k 11.0k
2.8k
AOU T+
2200 pF
BUFFERED CMOUT
2200 pF
14.0k
220 pF
3.3 3.3.1
Analog Outputs Line Level Outputs
3-Pole Butterworth Filter
The CS4812 contains on-chip differential buffer amplifiers that produce line level outputs capable
Figure 12. Butterworth Output Filters
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1 k From Op-Amp VA MMBT3906 MMBT3904 10 k 3.3 k 10 F +
Line Out
GND 10 k
From CS4812 PIO
10 k MMBT3906 10 F
tializes the hardware configuration registers and downloads the application code to the DSP via 2 dedicated control port registers. Application messaging between the host and the DSP is also done via these control port registers. The operation of the control port may be completely asynchronous to the audio sample rate. However, it is recommended that the control port pins remain static when not in use. The required control port register settings are contained in the Crystal effects firmware application code EEPROM image. The control port supports the SPI bus and the I2C(R) bus in both master and slave modes. The bus interface is selected via the SPI/I2C pin and the master/slave mode is selected via the SCPM/S pin. These pins are sampled during de-assertion of the RST pin. Master mode is selected for stand-alone operation when AutoBooting from an external serial EEPROM. Slave mode is selected when the CS4812 is connected to an external host controller.
Figure 13. Output Mute Circuit
3.4
Clock Generation
The CS4812 master clock may be generated by using the on-chip oscillator with an external crystal or may be derived from an external clock source.
3.4.1
Clock Source
The CS4812 requires a 256 Fs master clock to run the internal logic. The two possible clock sources are the on-chip crystal oscillator or an external clock input to the XTI pin. When using the on-chip crystal oscillator, external loading capacitors are required. (see Figure 5) High frequency crystals (>8 MHz) should be parallel resonant, fundamental mode and designed for 20 pF loading. (equivalent to 40 pF to ground on each leg)
3.5.1
SPI Bus
3.5
Serial Control Port
The serial control port contains all of the main control logic for the chip. It controls power-on sequencing, hardware configuration and DSP operation. In AutoBoot mode, the serial control port manages the entire boot process including initialization of its own hardware configuration registers from EEPROM, code download from the EEPROM to the DSP and initialization of the CODEC. In host-controlled mode, the host-device iniDS291PP3
The SPI bus interface consists of 5 digital signals, CCLK, CDIN, CDOUT, CS and REQ. CCLK, the control port bit clock, is used to clock individual data bits. CDIN, the control data input, is the serial data input line to the CS4812. CDOUT, the control data output, is the output data line from the CS4812. It is open-drain and requires a 2.2 k pull-up resistor. CS, the chip select signal, is asserted low to enable the SPI port. REQ, the request pin, is used by the DSP to request a read by a host controller when operating in control port slave mode. Data is clocked into the chip on the rising edge of CCLK and out on the falling edge. When in slave mode, the CLK signal must be synchronous with the internal DSP clock. An external D flip flop off of CLKOUT as shown in Figure 9 can be used to retime the CLK signal. There is limited drive capability on CLKOUT so
19
CS4812
a buffer may be required to minimize the capacitive loading on CLKOUT. CCLK and CS may be inputs or outputs with respect to the CS4812. If the serial control port of the CS4812 is defined as the master, then CCLK and CS are outputs and CCLK requires a 2.2 k pull-up resistor. If the CS4812 is defined as the slave, then CCLK and CS are inputs and no pull-up resistor is required on CCLK. The 8-bit read instruction (00000011) is sent to the EEPROM followed by a pre-defined 16-bit start address.The CS4812 then automatically clocks out sequential bytes from the EEPROM until the last byte has been received. After the last byte is received, the CS4812 deasserts CS and begins program execution. At this point, the serial control port becomes inactive until the next reset.
3.5.1.2
SPI Slave Mode
3.5.1.1
SPI Master Mode
The SPI master mode is designed for read-only operation during AutoBooting from a serial EEPROM. A typical AutoBoot sequence with a Xicor X25650 serial EEPROM, or equivalent, is shown in Figure 14. On exit from reset, the CS4812 asserts CS.
CS
0 1 23 4 56 7 8 9 10 11
In SPI slave mode, a write sequence from an external host controller is shown in Figure 15. The host controller asserts CS and sends a 16-bit write preamble to the CS4812. This preamble consists of a 7-bit chip address (must be 0010000) followed by a one-bit R/W (Read/Write) bit (set to 0 for write)
21 22 23 24 25 26 27 28 29 30 31
CLK
DATA DATA + n
76 5 4 3 2 10
CDIN
READ COMMAND 16-BIT ADDRESS = 0X0000
0 11 00 00 000
76
5
4
3 2 10
CDOUT
00
0
0
0
MSB
Figure 14. Control Port Timing, SPI Master Mode AutoBoot
CS
(input) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
(input)
CHIP ADDRESS (WRITE)
MAP BYTE
INCR
DATA
2 1 0 7 6 5 4 3 2 1 0 7 6 5
DATA +n
4 3 2 1 0
CDIN
(input)
0
0
1
0
0
0
0
0
6
5
4
3
MSB
R/W
CDOUT
(output)
Figure 15. Control Port Timing, SPI Slave Mode Write
20
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CS4812
and a memory address pointer (MAP) byte. The MAP byte contains the address of the control port register to be accessed. Following the preamble, the host controller sends the actual data byte to be written to the register designated by the MAP. The host controller then de-asserts CS. Figure 16 shows the SPI slave mode write flow diagram. In SPI slave mode, a read sequence from an external controller is shown in Figure 17. The host controller executes a partial write-cycle by sending a 16-bit write preamble to the CS4812 with the MAP byte set to the address of the control port byte register to be read. The host controller then de-asserts CS, re-asserts CS, and sends the 7-bit chip address followed by the R/W bit set to 1. The host controller then clocks out the control port register designated by the MAP byte. The host controller then de-asserts CS. Figure 18 shows the SPI mode slave read flow diagram initiated by the host microcontroller. Figure 19 shows the SPI slave mode read flow diagram incorporating the DSP REQ signal. REQ is used to notify the host controller that a data byte from the DSP is waiting to be read. The behavior of the REQ signal is dependent on when data is written to the serial control port output register in relation to CCLK and bit 2 of the current byte being transferred. There are three cases of REQ behavior:
Y
SET CS LOW
WRITE ADDRESS BYTE WITH R/W BIT = 0
WRITE MAP BYTE
WRITE DATA BYTE
MORE DATA?
N SET CS HIGH
Figure 16. SPI Slave Write Flow Diagram
1. The REQ line will be de-asserted immediately following the rising edge of CCLK on the D2 bit of the current byte being transferred if there is no data in the serial control port output register. The REQ line remains de-asserted and a stop condition
CS
(input) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK
(input)
CHIP ADDRESS (WRITE)
MAP BYTE
INCR
CHIP ADDRESS (READ)
1 0 0 0 1 0 0 0 0 1
CDIN
(input)
0
0
1
0
0
0
0
0
6
5
4
3
2
MSB
R/W
R/W DATA DATA
2 1 0 7 6 5 4 3 2 1 0
CDOUT
(output)
7
6
5
4
3
REQ
(output)
Figure 17. Control Port Timing, SPI Slave Mode Read
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CS4812
N
REQ LOW?
SET CS LOW Y WRITE ADDRESS BYTE WITH R/W BIT = 0 WRITE ADDRESS BYTE WRITE MAP BYTE WITH R/W BIT = 0 SET CS LOW
TOGGLE CS
WRITE MAP BYTE FOR DSP OUTPUT REGISTER (MAP = 0X27)
WRITE ADDRESS BYTE WITH R/W BIT = 1 TOGGLE CS
WRITE ADDRESS BYTE READ DATA BYTE WITH R/W BIT = 1
MORE BYTES TO READ?
N SET CS HIGH
Y
READ DATA BYTE FROM DSP OUTPUT REGISTER
REQ STILL LOW?
N SET CS HIGH
Y
Figure 18. SPI Slave Mode Read Flow Diagram
Figure 19. SPI Slave Mode Read from DSP Core Flow Diagram using DSP REQ
should be issued by the bus master, thus completing the transfer. 2. If data is written to the serial control port output register prior to the rising edge of CCLK for the D2 data bit, REQ will remain asserted. The bus master should continue to shift out this new byte. 3. If data is placed in the SCP output register by the DSP after the rising edge of CCLK for the D2 bit, REQ will be immediately re-asserted, thus creating a pulse on REQ. The byte in the SCP out register may be read by the bus master as part of the current transaction or may be read later as part of a new read transaction.
22
The CS4812 has a MAP auto increment capability which allows block reads or writes of successive control port registers.This feature is enabled by setting the INCR bit in the MAP byte. During a write sequence, multiple bytes may be written by continuing to send data bytes to the CS4812 after the first data byte and before de-asserting CS. If auto increment is disabled, the last data byte sent will appear in the register designated by the MAP. If auto increment is enabled, data bytes sent following the first data byte will be written to successive registers following that designated in the MAP.
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CS4812
During a read sequence, multiple bytes may be read by continuing to clock out data bytes to the CS4812 after the first data byte and before de-asserting CS. If auto increment is disabled, the last data byte read will be the register designated by the MAP. If auto increment is enabled, data bytes read following the first data byte will be read from successive registers following that designated in the MAP. a slave device and may be tied to ground when the CS4812 is configured for master mode. When operating in control port slave mode, the REQ output pin is used by the CS4812 DSP to request communication with the master.
3.5.2.1
I2C Master Mode
3.5.2
I2C Bus
The I2C bus interface implemented on the CS4812 consists of 3 digital signals, SCL, SDA and REQ. SCL, or serial clock, is used to clock individual data bits. SDA, or serial data, is a bidirectional data line. REQ, the request pin, is used by the DSP to request a host read when operating in control port slave mode. Two additional pins, AD1 and AD0, are inputs which determine the 2 lowest order bits of the 7-bit I2C device address. SCL may be defined as an input or an output with respect to the CS4812. If the serial control port of the CS4812 is defined as the master, then SCL is an open-drain output and requires a pull-up resistor as shown in Figure 5. Conversely, if the serial control port of the CS4812 is defined as the slave, then SCL is an input. SDA carries time-multiplexed bidirectional serial data. It is open-drain and requires a pull-up resistor as shown in Figure 5. AD1 and AD0, the inputs which determine the 2 lowest order bits of the 8-bit I2C device address, are meaningful only when the CS4812 is operating as
The I2C master mode is designed for read-only operation during AutoBooting from a serial EEPROM. A typical AutoBoot sequence with a Microchip X24256 serial EEPROM, or equivalent, is shown in Figure 20. On exit from reset, the CS4812 sends an initial write preamble to the EEPROM which consists of a I2C start condition and the slave address byte. The slave address consists of the 4 most significant bits set to 1010, the following 3 bits corresponding to the device select bits, A2, A1 and A0 set to 000 and the last bit (R/W) set to 0. Following this, a 2-byte EEPROM starting address of 0x0000 is sent to the EEPROM. The 2byte EEPROM starting address uses only the lowest 13 bits and sets the highest 3 bits to zero. To begin reading from the EEPROM, the CS4812 sends another start condition followed by a read preamble. The read preamble is identical to the write preamble except for the state of the R/W bit. The CS4812 then automatically clocks out sequential bytes from the EEPROM until the last byte has been received. These bytes include initial values for all control port registers as well as the DSP application code. After the last byte, the CS4812 initiates a stop condition and begins program execution. At this point, the serial control port becomes inactive until the next reset. Actual EE-
0
1
2
3
4
5
6
7
8
9
10
16 17 18 19
25 26 27 28 29 30 31 32 33 34 35 36 37
SCL
CHIP ADDRESS (WRITE) MEMORY ADDRESS
0 0 0 0 0 0 1
CHIP ADDRESS (READ)
0 1 0 A2 A1 A0 1
DATA
7 0
DATA +n
7 0
SDA
START
1
0
1
0
A 2 A1 A0 0
ACK
ACK
ACK START
ACK
NO ACK STOP
Figure 20. Control Port Timing, I2C Master Mode AutoBoot
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CS4812
PROM memory mapping is handled automatically by the development tools and is transparent to the designer.
SEND I2C START
3.5.2.2
I2C Slave Mode
WRITE ADDRESS BYTE WITH R/W BIT = 0
In I2C slave mode, a write sequence from an external host controller is shown in Figure 22.. The host controller sends a write preamble consisting of a start condition followed by the slave address for the CS4812. The slave address byte consists of a 7-bit address field (00100|AD1|AD0) followed by a Read/Write bit (set to 0). AD1 and AD0 correspond to the logic levels applied to the these pins on the CS4812. The host controller then sends a MAP byte which contains the address of the control register to be accessed followed by the actual data byte to be written to the register designated by the MAP. Upon completion of this, the host controller then sends a stop condition to complete the transaction. Figure 21 shows the I2C slave mode write flow diagram In I2C slave mode, a read sequence by an external host controller is shown in Figure 23. The host controller sends a write preamble to the CS4812 which
GET ACK
SEND MAP BYTE
GET ACK
SEND DATABYTE
GET ACK
Y MORE DATA? N SEND I2C STOP
Figure 21. I2C Slave Mode Write Flow Diagram
19 24 25 26 27 28
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
DATA
2 1 0 7 6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
START
0
0
1
0
0 AD1 AD0 0
6
5
4
3
ACK
ACK
ACK
ACK STOP
Figure 22. Control Port Timing, I2C Slave Mode Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
CHIP ADDRESS (READ)
1 0 0 0 1 0 0 AD1 AD0 1
DATA
7 0
DATA +1
7 0
DATA + n
7 0
SDA
START
0
0
1
0
0 AD1 AD0 0
6
5
4
3
2
ACK
ACK START
ACK
ACK
NO ACK STOP
REQ
Figure 23. Control Port Timing, I2C Slave Mode Read
24
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CS4812
consists of a start condition followed by its slave address byte with the Read/Write bit set to 0. The host controller then initiates a read preamble. The read preamble is identical to the write preamble except for the state of the Read/Write bit. The host controller then sends a MAP byte which contains the address of the control register to be accessed. After receiving the MAP byte, the CS4812 returns the contents of this register to the host controller. The host controller may continue reading registers by sending additional MAP bytes or complete the transaction by initiating a stop condition. Figure 24 shows the SPI mode slave read flow diagram initiated by the host microcontroller. Figure 25 shows the I2C slave mode read flow diagram incorporating the DSP REQ signal. REQ is used to notify the host controller that a data byte from the DSP is waiting to be read. The behavior of the REQ signal is dependent on when data is written to the SCP output register in relation to SCL and bit 1 of the current byte being transferred. There are three cases of REQ behavior: 1. The REQ line will be de-asserted immediately following the rising edge of SCL on the D1 bit of the current byte being transferred if there is no data in the SCP output register. The REQ line remains de-asserted and a stop condition should be issued by the bus master, thus completing the transfer. 2. If data is written to the SCP output register prior to the rising edge of SCL for the D1 bit, REQ will remain asserted. The bus master should continue to shift out this new byte. 3. If data is placed in the SCP output register by the DSP after the rising edge of SCL for the D1 bit, REQ will be immediately re-asserted, thus creating a pulse on REQ. The byte in the SCP out register may be read by the bus master as part of the current transaction or may be read later as part of a new read transaction. The CS4812 has a MAP auto increment capability which allows block reads or writes of successive
DS291PP3
SEND I2C START
WRITE ADDRESS BYTE WITH R/W BIT = 0
GET ACK
SEND MAP BYTE
GET ACK
SEND I2C START
WRITE ADDRESS BYTE WITH R/W BIT = 1
GET ACK
READ DATABYTE
MORE BYTES TO READ? N SEND NACK
Y SEND ACK
SEND I2C STOP
Figure 24. I2C Slave Mode Read Flow Diagram
control port registers.This feature is enabled by setting the INCR bit in the MAP byte. During a write sequence, multiple bytes may be written by continuing to send data bytes to the CS4812 after the first data byte and before initiating a stop condition. If auto increment is disabled, the last data byte sent will appear in the register designated by the MAP. If auto increment is en25
CS4812
abled, data bytes sent following the first data byte will be written to successive registers following that designated in the MAP.
N
REQ LOW?
Y
SEND I2C START
WRITE ADDRESS BYTE WITH R/W BIT = 0
During a read sequence, multiple bytes may be read by continuing to clock in data bytes to the CS4812 after the first data byte and before initiating a stop condition. If auto increment is disabled, the last data byte read will be the register designated by the MAP. If auto increment is enabled, data bytes read following the first data byte will be read from successive registers following that designated in the MAP.
GET ACK
3.6
SEND MAP BYTE
Boot Modes
GET ACK
SEND I2C START
WRITE ADDRESS BYTE WITH R/W BIT = 1
GET ACK
There are two different techniques that allow the system to load the application code into the CS4812. The first technique is called, "AutoBoot" and allows the application code to be loaded from an external serial EEPROM with an I2C or SPI interface. This technique is used in system applications that due not have a host. The second technique is called, "Host Boot" and allows the application code to be loaded directly from the host microcontroller via I2C or SPI communication interface. This method may eliminate the need for an external EEPROM.
3.6.1
READ DATABYTE
AutoBoot
Y REQ STILL LOW? N SEND NACK SEND ACK
SEND I2C STOP
The AutoBoot method simply requires an external EEPROM with an I2C or SPI serial bus interface. The DSP, automatically loads and runs the application code resident in the EEPROM upon deassertion of the RESET line. It should be noted that this technique is used for systems that do not have a microcontroller and do not require real-time adjustment of the application code parameters. Please refer to Table 10 on page 6 for the timing requirements of the RESET line.
Figure 25. I2C Slave Mode Read from DSP Core Flow Diagram with DSP REQ
3.6.2
HostBoot
By using the HostBoot technique, an external microcontroller is required to download the applica-
26
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CS4812
tion code. This technique allows for real-time control of all parameters specific to the application code. Please refer to Figure 26 for the HostBoot procedure flow chart and to Section 1.2.1 of AN195 for an example of a host boot sequence.
SEND APPLICATION SPECIFIC CONTROL PORT CONFIG BYTES
3.7
Resets
WRITE BYTE 0XA4 TO CONTROL PORT REGISTER 4 (MAP = 4)
There are several reset mechanisms in the CS4812 which affect different parts of the chip. Full chip reset can only be achieved by asserting the external RST pin. With RST asserted, the chip enters low power mode during which the control port, CODEC and DSP are reset, all registers are returned to their default values and the DAC outputs are muted. The RST pin should be asserted during powerup until the power supplies have reached steady state. If the supply voltage drops below 4 Volts, the CODEC is reset, the DAC outputs are muted and the DSP automatically executes a soft reset. Upon exit from a CODEC reset, the DSP restarts the application code and the CODEC performs the following procedure:
- The CODEC resynchronizes. - The DAC outputs unmute.
WRITE BYTE 0XA5 TO CONTROL PORT REGISTER 4
WRITE BYTE 0XA7 TO CONTROL PORT REGISTER 4
SEND 3 BYTE MESSAGE TO THE DSP INPUT REGISTER (MAP = 3) :0X000004
WAIT FOR REPLY FROM DSP (REQ LINE GOES LOW)
READ REPLY BYTE FROM DSP OUTPUT REGISTER (MAP = 27)
REPLY BYTE = 0X01?
Y
N
WRITE .LDT FILE INTO DSP INPUT REGISTER (MAP = 16) (LOAD APPLICATION CODE)
N
REQ LOW?
Y
READ REPLY BYTE FROM DSP OUTPUT REGISTER (MAP = 27)
REPLY BYTE = 0X02?
Y
N
SEND 3 BYTE MESSAGE TO THE DSP INPUT REGISTER (MAP = 16):0X000005
WRITE BYTE 0XA6 TO CONTROL PORT REGISTER 4
Figure 26. HostBoot Flow Diagram
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CS4812
4. POWER SUPPLY AND GROUNDING
Proper layout and grounding is critical to obtaining optimal audio performance in your system. The most important rule to remember is to not allow currents from digital circuitry to couple into sensitive analog circuitry. This is generally done by using a separate or filtered power supply for the analog circuitry, physically separating the analog and digital components and traces in the pcb layout and using wide traces or planes for ground and power. One misplaced component or trace can severely degrade overall system performance. When using separate supplies, the analog and digital power should be connected to the CS4812 via a ferrite bead, positioned closer than 1" to the device (see Figure 21). The CS4812 VA pin should be derived from the quietest power source available. If only one supply is available, use the suggested arrangement in Figure 5. A single solid ground plane is the simplest grounding scheme that works well in many cases. All analog and digital grounds shown in Figure 5 should be tied to the one plane. Decoupling capacitors should be placed as close as possible to the device with the lowest value capacitor closest to the chip. Any power and ground connection vias should be placed near their respective component pins and should be attached directly to the appropriate plane. If traces are used for the power supplies to the CS4812, they should be as wide as possible to maintain low impedance. It is recommended to solder the CS4812 directly to the printed circuit board. Soldering improves performance and enhances reliability
> 1/8"
Digital Power Plane
Ferrite Bead
Note that the CS4812 is oriented with its digital pins towards the digital end of the board.
CS4812
Analog Power Plane
Digital Interface
Analog Signals & Components
Figure 27. CS4812 Suggested Layout
28
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CS4812
5. PIN DESCRIPTIONS
DGND AD1/CDIN AD0/CS SPI/I2C SCPM/S REQ RST RES-VD NC NC NC NC NC NC NC NC RES-DGND RES-DGND NC NC AINL+ AINLVA AGND AINR+ AINRCMOUT CMFILT+ CMFILTRES-NC RES-DGND RES-NC NC NC NC NC NC NC NC NC NC AOUT1+ AOUT1AOUT2+ AOUT2AGND VA AGND RES-NC RES-NC VD DGND SCL/CCLK SDA/CDOUT RES-NC RES-NC RES-NC RES-NC RES-NC NC NC NC NC NC NC NC NC RES-DGND CLKOUT XTO XTI DGND VD DGND PIO0 PIO1 OVL RES-DGND PIO2 RES-DGND PIO3 RES-DGND NC RES-DGND NC NC NC NC NC NC NC NC RES-NC RES-NC RES-NC RES-NC AGND VA RES-NC RES-NC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
CS4812 100-PIN MQFP
Figure 28. Pin Assignments
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CS4812
Power Supply
VA - Analog Power Power: analog supply, +5V. AGND - Analog Ground Ground: analog ground. VD - Digital Power Power: digital supply, +5V. DGND - Digital Ground Ground: digital ground.
Analog Inputs
AINL+/-,AINR+/- - Differential Analog Inputs Inputs: These pins accept differential analog input signals and are internally biased to the reference voltage of 2.3 V. The + and - input signals should be 180 out of phase. A single-ended signal may also be directly applied to either the + or - input with the other input AC coupled to ground through a capacitor. In general, differential input signals provide better performance. For best audio performance, a passive anti-aliasing filter is required. The typical connection diagram in Figure 5. shows the recommended single-ended input circuit. Figure 10 shows the recommended differential input circuit. Inputs may be externally AC or DC coupled. This permits use of the ADCs for input of audio signals or for measurement of DC control voltages. By default, an internal high pass filter removes any DC offsets from both of the ADC inputs. If measurement of DC is required on either of the ADC inputs, then the internal high pass filter must be disabled. Analog audio input signals that are DC coupled must be biased at 2.3 V to maintain proper input signal swing. DC control input voltages may range from ground to Vcc and should be applied to only the + or - input with the other input coupled to ground through a capacitor. OVL - ADC Overload Indicator Output: This pin is asserted if either ADC is clipping. The pin does not latch and de-asserts when clipping stops.
Analog Outputs
AOUT1+/-, AOUT2+/- - Differential Audio Outputs Outputs: These pins output differential analog signals which are biased to the internal reference voltage of approximately 2.3V. The + and - output signals are 180 out of phase resulting in a nominal differential output voltage of twice the output pin voltage. For best performance, an anti-imaging filter is required. Figure 12 shows the recommended second and third order Butterworth differential-to-singleended output buffer circuits.
Voltage Reference
CMOUT - Common Mode Output Output: This pin provides an internally generated reference of 2.3V to be used for biasing external analog circuitry. The load on CMOUT must be DC only, with an impedance of not less than 50 k. CMFILT+,CMFILT- - Common Mode Filter Connections Inputs: These pins are connections for external filter components required by the internal common mode reference circuit. See the typical connection diagram in Figure 5. for details.
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CS4812
Serial Control Port
SCPM/S - Serial Control Port Master/Slave Select Input: This pin configures the serial control port as a master if tied to VD or a slave if tied to DGND. SPI/I2C - Serial Control Port Format Select Input: This pin configures the control port for I2C format if tied to VD or SPI format if tied to DGND. SCL/CCLK - Serial Control Port Clock Bidirectional: This pin clocks serial control port data into and out of SDA in I2C mode. In SPI mode, it clocks control port data into CDIN and out of CDOUT. When the serial control port is configured as a master, SCL/CCLK is an output and is generated internally. When the serial control port is configured as a slave, SCL/CCLK is an input and may operate asynchronously to the master clock. AD0/CS - I2C Address Bit 0 / SPI Chip Select Bidirectional: In I2C(R) mode, AD0 is an input and defines bit 0 of the partial chip address. The upper 5 bits of the 7-bit address must be 00100. In SPI mode, CS is the chip select pin. When the serial control port is defined as a master in SPI mode, CS is an output. When the serial control port is defined as a slave in SPI mode, CS is an input. AD1/CDIN - I2C Address Bit 1 / SPI Data Input Input: In I2C(R) mode, AD1 is an input and defines bit 1 of the partial chip address. The upper 5 bits of the 7-bit address must be 00100. In SPI mode, CDIN is the serial control port data input and is clocked in on the rising edge of CCLK. SDA/CDOUT - I2C Data / SPI Data Output Bidirectional: In I2C(R) mode, SDA is the bidirectional data I/O line. In SPI mode, CDOUT is the serial control port data output and is clocked out on the falling edge of CCLK. REQ - DSP Output Request Output: This pin is used when the serial control port is configured for slave mode operation. This pin is asserted when the DSP has written a byte to a register in the control port. When this register is read by the master device, REQ is de-asserted.
Clock and Crystal
XTI, XTO - Crystal Oscillator Connections (Master Clock) Input, Output: These pins provide connections for an external parallel resonant quartz crystal. Alternately, an external clock source may be applied to XTI. The clock frequency must be 256xFs. CLKOUT - Clock Output Output: This pin provides a clock output which can be used to synchronize external components. Available output frequencies 1xFs, 128xFs and 256xFs are selectable via a control port register. The default frequency is 256xFs. It is recommended to externally buffer this signal with a CMOS gate as shown in Figure 5.
Miscellaneous
PIO0:3 - General Purpose Inputs/Outputs Bidirectional: These pins are general-purpose digital I/O pins. The Default state is input. The functionality of these pins after boot-up is determined by the application firmware code loaded into the device during the boot-up process. RST - Reset Input: This pin causes the device to enter a low power mode and forces all control port and i/o registers to be reset to their default values. The control port can not be accessed when reset is low.
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31
CS4812
NC - No Connect Input: These pins are not internally connected and should be tied to ground for optimal performance. RES-NC - Reserved, No Connect These pins are reserved and must be left unconnected for normal operation. RES-VD - Reserved, Connect to VD These pins are reserved and must be tied to VD for normal operation. RES-DGND - Reserved, Connect to DGND These pins are reserved and must be tied to digital ground for normal operation. RES-AGND - Reserved, Connect to AGND These pins are reserved and must be tied to analog ground for normal operation.
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CS4812
6. PARAMETER DEFINITIONS
Dynamic Range The ratio of the full scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbFs signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Total Harmonic Distortion + Noise The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 20 Hz to 20 kHz), including distortion components. Expressed in decibels. ADCs are measured at -1dBFs as suggested in AES 17-1991 Annex A. Idle Channel Noise / Signal-to-Noise-Ratio The ratio of the RMS analog output level with 1kHz full scale digital input to the RMS analog output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio. Total Harmonic Distortion (THD) THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of the test signal. Units in decibels. Interchannel Isolation A measure of crosstalk between channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Frequency Response A measure of the amplitude response variation from 20Hz to 20kHz relative to the amplitude response at 1kHz. Units in decibels. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in decibels. Gain Error The deviation from the nominal full scale output for a full scale input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input grounded. For the DACs, the deviation of the output from zero (relative to CMOUT) with mid-scale input code. Units are in volts.
DS291PP3
33
CS4812
7. PACKAGE DIMENSIONS
100L MQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
INCHES MIN MAX --0.134 0.010 0.014 0.009 0.015 0.667 0.687 0.547 0.555 0.904 0.923 0.783 0.791 0.022 0.030 0.000 7.000 L 0.018 0.030 * Nominal pin pitch is 0.65 mm DIM A A1 B D D1 E E1 e* Controlling dimension is mm. JEDEC Designation: MS022 MILLIMETERS MIN MAX --3.400 0.250 0.350 0.220 0.380 16.950 17.450 13.900 14.100 22.950 23.450 19.900 20.100 0.550 0.750 0.00 7.00 0.450 0.750
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DS291PP3
* Notes *

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